1. Field of the Invention
The present invention is directed to integrated circuits and, more particuarly, to input circuits used in combination with high speed busses.
2. Description of the Background
Communication busses have been developed which can transmit signals between circuitry at a rate that is faster than the capacity of many integrated circuits. Thus, the data transmission rate of modern systems comprised of integrated circuits is primarily limited by internal circuitry operating speeds. To address the need for faster circuits, a group of integrated circuits can be combined on a common bus. In that configuration, each integrated circuit operates in a coordinated manner with the other integrated circuits to share data which is transmitted at a high speed. For example, a group of memory devices, such as random access memories (RAMs), dynamic random access memories (DRAMs), or read only memories (ROM), can be connected to a common data bus. The bandwidth of the bus is typically greater than the bandwidth of an individual memory device due to the operation of memory devices in parallel. Each memory device, therefore, is operated so that while one memory is processing received data, another memory is receiving new data. By providing an appropriate number of memory devices and an efficient control system, very high speed data transmissions can be achieved.
As the transmission rate of high speed busses continues to increase, more stringent operating parameters are imposed on the integrated circuits, such as memory devices, connected thereto. The specification for a high speed bus typically identifies a required xe2x80x9csetupxe2x80x9d time and xe2x80x9choldxe2x80x9d time. The setup time is the time allotted, prior to a clock edge used to capture information related to a bus transaction (i.e., command, address, and data), for the information to arrive at a destination. The ADT Bus Specification, for example, allows a setup time on the order of 200 to 250 pico-seconds from the time data (e.g., address, data, command, etc.) is valid before the next clock transition. Once bus transaction information is made available, the ADT Bus Specification allows for a hold time on the order of 200 to 250 pico-seconds. The failure to meet the setup time and hold time requirements may lead to the capturing of invalid bus transaction information. Although there are numerous latch and register circuits used to receive and hold data, the need exits for improved circuits capable of meeting the low setup time and hold time requirements.
The present invention is directed to a circuit having a data input pin for receiving a data signal, a clock input pin for receiving a clock signal and having a low setup time and a zero hold time. The circuit is comprised of an input stage for periodically connecting a sampling device to the data input pin in response to the clock signal. An evaluation stage, responsive to the clock signal, evaluates the charge collected by the sampling device at a time the device is disconnected from the data input pin. The evaluation stage produces a signal representative of the sampled charge. An output stage, responsive to the clock signal and the produced signal, outputs a data signal representative of the sampled charge, i.e., the sampled data signal. The circuit may have a single data path and a single charge accumulating device such that an output signal representative of the sampled data signal is available on either the rising or the falling edge of the clock signal. Alternatively, multiple data paths may be provided as well as multiple charge accumulating devices so that data signals representative of the sampled data may be output on both the rising and the falling edge of the clock signal. Various types of components may be implemented in the design such that the circuit can be operated as either a latch or a register. The circuit of the present invention may be used as a command or data latch in, for example, various memory devices connected to a high speed system bus.
The present invention is also directed to a method of operating a data acquisition and retention circuit having a low setup time and a zero hold time and of the type useful for receiving signals from a high speed bus. The method is comprised of the steps of connecting a charge accumulating device to a source of data signals in response to an edge of a clock signal. The charge accumulating device is isolated from the source of data signals in response to another edge of the clock signal. The accumulated charge is evaluated at the time when the device is isolated from the source of data signals. A logic signal, i.e. data signal, is output based on the evaluating step. The connecting and isolating steps may each last for approximately one half of the cycle of the clock signal, or approximately one nano-second.
The circuit disclosed herein may be implemented as a latch or register that has a very low setup time (less than 50 ps) and zero hold time. That level of performance is achieved in several ways. First, the clock and data paths are carefully matched in terms of topology, loading and delay. Second, the amount of charge required to setup the data state is kept very low. Third, the data path is isolated prior to the pre-charge and evaluate latch firing to eliminate any hold time requirements. The combination of those features, and others, allows the present invention to achieve very low setup and zero hold time performance. Because the circuit of the present invention has such a low setup time and requires zero hold time, the 200-250 pico-second system performance time can be used by other parts of the device in which the circuit of the present invention may be employed. Those, and other advantages and benefits, will be apparent from the Description of the Preferred Embodiment appearing hereinbelow.